DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 46

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

6.5
The following sections provide examples of typical configurations for the MB86064 and required
register settings. In all cases other registers are assumed to be at their default values, following a
device reset.
6.5.1 Dual DAC, LVDS data, Clock Outputs enabled
6.5.2 Single DAC, LVDS data port A, driving DAC A
6.5.3 Multiplexed LVDS data into DAC A (A=EVEN, B=ODD)
6.5.4 Waveform Memory Module, Different A & B Waveforms
Page 46 of 52
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
• 0x1B2
• 0x1C3
• 0x1B2
• 0x1C0
• 0x1C3
• 0x00
• 0x21
• 0x1B2
• 0x1C0
• 0x1C3
• 0x1C4
• 0x10
• 0x20
• 0x1B2
• 0x1C3
• 0x1C4
Example Setup Register Settings
Address
Address
Address
Address
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Data
0x0000000
0x00001C0
Data
0x0000000
0x0000002
0x0000BC0
Data
0x10
0x01
0x0000000
0x0000002
0x00009C0
0x0000080
Data
0x00
0x00
0x0000000
0x00007E0
0x0000081
Production
Note
set recommended DAC core delay settings
power up device and enable clock outputs
Note
set recommended DAC core delay settings
set Iref for DAC A only configuration
power up DAC A and enable clock outputs
Note
set WMM/LVDS data mux to WMM
set ODD Mux0 = Mux1 data
set recommended DAC core delay settings
set Iref for DAC A only configuration
power up data ports, DAC A and clock outputs
enable WMM clock (bit #1 to ‘0’)
Note
enable EVEN memory
enable ODD memory
set recommended DAC core delay settings
power up both DACs, disable LVDS ports
enable WMM clock, disable clock outputs
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
MB86064 Dual 14-bit 1GSa/s DAC
October 2005 Version 1.2
FME/MS/DAC80/DS/4972