EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 133

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 5–18. Multiply Accumulate Mode Shown for Half-DSP Block
Altera Corporation
October 2007
accum_sload
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
Multiply Accumulate Mode
In multiply accumulate mode, the second-stage adder is configured as a
44-bit accumulator or subtractor. The output of the DSP block is looped
back to the second-stage adder and added or subtracted with the two
outputs of the first-stage adder block according to
Figure 5–18
accumulate mode.
+
+
output_saturate
shows the DSP block configured to operate in multiply
output_round
signa
signb
+
Stratix III Device Handbook, Volume 1
chainout_sat_overflow
DSP Blocks in Stratix III Devices
Equation
44
5–3.
result[ ]
5–33