EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 461

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Boundary-Scan
Description
Language
(BSDL) Support
Conclusion
Referenced
Documents
Altera Corporation
November 2007
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The Boundary-Scan Description Language (BSDL), a subset of VHDL,
provides a syntax that allows you to describe the features of an IEEE Std.
1149.1 BST-capable device that can be tested. Test software development
systems then use the BSDL files for test generation, analysis, and failure
diagnostics.
For more information on BSDL files for IEEE Std. 1149.1-compliant
Stratix III devices and the BSDLCustomizer script, visit the Altera web
site at www.altera.com.
The IEEE Std. 1149.1 BST circuitry available in Stratix III devices provides
a cost-effective and efficient way to test systems that contain devices with
tight lead spacing. Circuit boards with Altera and other IEEE Std.
1149.1-compliant devices can use the EXTEST, SAMPLE/PRELOAD, and
BYPASS modes to create serial patterns that internally test the pin
connections between devices and check device operation.
This chapter references the following documents:
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Perform a SAMPLE/PRELOAD test cycle prior to the first EXTEST test
cycle to ensure that known data is present at the device pins when
you enter the EXTEST mode. If the OEJ update register contains a 0,
the data in the OUTJ update register is driven out. The state must be
known and correct to avoid contention with other devices in the
system.
Do not perform EXTEST testing during ICR. This instruction is
supported before or after ICR, but not during ICR. Use the
CONFIG_IO instruction to interrupt configuration and then perform
testing, or wait for configuration to complete.
If performing testing before configuration, hold the nCONFIG pin
low.
Bleeker, H., P. van den Eijnden, and F. de Jong. Boundary-Scan Test:
A Practical Approach. Eindhoven, The Netherlands: Kluwer
Academic Publishers, 1993.
Configuring Stratix III Devices
Device Handbook
Hot Socketing and Power-On Reset in Stratix III Devices
volume 1 of the Stratix III Device Handbook
For more information on boundary scan testing, contact Altera
Applications.
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
chapter of volume 1 of the Stratix III
Stratix III Device Handbook, Volume 1
chapter of
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