EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 542

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
Figure 1–3. Output Register Clock to Output Timing Diagram
1–30
Stratix III Device Handbook, Volume 2
Datain
Clock
Clock pad to output
Register delay
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
using values from
2.
3.
load, using the appropriate IBIS model or capacitance value to represent
the load.
4.
5.
delay should be added to or subtracted from the I/O Standard Output
Adder delays to yield the actual worst-case propagation delay (clock-to-
output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 1–35
circuit that is represented by the output timing of the Quartus II software.
Simulate the output driver of choice into the generalized test setup,
Record the time to V
Simulate the output driver of choice into the actual PCB trace and
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
using the above equation.
Output Register
Table
micro t
1–35.
MEAS
MEAS
CO
.
.
Output Register to
output pin delay
Figure 1–4
shows the model of the
Altera Corporation
Output
November 2007