EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 146

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Application Examples
5–46
Stratix III Device Handbook, Volume 1
When you use both the input cascade and chainout features, the DSP
block uses an 18-bit delay register in the boundary of each half-DSP block
or from block-to-block to synchronize the input scan chain data with the
chainout data. The top half computes the sum of product and chains the
output to the next block after the output register. The output register uses
the delay register to delay the cascade input by one clock cycle to
compensate the latency for the bottom half.
For applications in which the system clock is slower than the speed of the
DSP block, the multipliers can be time-multiplexed to improve efficiency.
This makes multi-channel and semi-parallel FIR structures possible. The
structure to achieve this is similar to
difference is that the input cascade chain is no longer used and each
half-DSP block is used in Four-Multiplier Mode with independent inputs.
Figure 5–23
In most cases, only the final stage FIR tap with the rounding and
saturation unit is deployed.
shows an example for chained cascaded summation.
Figures 5–21
and 5–22. The main
Altera Corporation
October 2007