EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 357

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 10–3. Simplified POR Block Diagram
Altera Corporation
October 2007
VCC
VCCL
PORSEL
VCCPT
VCCPGM
VCCPD
Regulator POR
Satellite POR
Main POR
The POR block consists of a regulator POR, satellite POR, and main POR
to check the power supply levels for proper device configuration. The
satellite POR monitors V
the configuration buffers for device programming. The POR block also
checks for functionality of I/O level shifters powered by V
V
supplies used in core. The internal configuration memory supply, which
is used during device configuration, is checked by the regulator POR
block and is gated in the main POR block for the final POR trip. A
simplified block diagram of the POR block is shown in
1
CCPGM
during power-up mode. The main POR checks the V
All configuration-related dedicated and dual function I/O pins
must be powered by V
Hot Socketing and Power-On Reset in Stratix III Devices
CCPD
and V
CCPGM
CCPGM
Stratix III Device Handbook, Volume 1
.
(12ms or 100ms)
power supplies that are used in
POR PULSE
SETTING
Figure
CCPD
POR
CC
10–3.
and V
and
10–5
CCL