EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 176

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
Figure 6–17. Stratix III PLL Block Diagram
Notes to
(1)
(2)
(3)
(4)
6–26
Stratix III Device Handbook, Volume 1
from adjacent PLL
GCLK/RCLK
The number of post scale counters is 7 for Left/Right PLLs and 10 for Top/Bottom PLLs.
This is the VCO post-scale counter
The FBOUT port is fed by the M counter in Stratix III PLLs.
The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a pin-driven global
or regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin driven dedicated global or regional clock. An internally generated global signal or general purpose I/O
pin cannot drive the PLL.
Cascade input
Clock inputs
pfdena
from pins
Figure
(4)
6–17:
4
inclk0
inclk1
Switchover
PLL Clock I/O Pins
Each Top/Bottom PLL supports six clock I/O pins, organized as three
pairs of pins:
■
■
■
Figure 6–18
Clock
Block
1st pair: 2 single-ended I/O or 1 differential I/O
2nd pair: 2 single-ended I/O or 1 differential external feedback input
(FBp/FBn)
3rd pair: 2 single-ended I/O or 1 differential input
K
÷n
clkswitch
clkbad0
clkbad1
activeclock
.
shows the clock I/O pins associated with Top/Bottom PLLs.
PFD
Circuit
Lock
CP
locked
LF
VCO
8
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(2)
To DPA block on
Left/Right PLLs
/2, /4
8
8
÷C0
÷C1
÷C2
÷C3
÷Cn
÷m
(1)
Altera Corporation
November 2007
Casade output
to adjacent PLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
GCLKs
RCLKs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT (3)
External
memory
interface DLL
External clock
outputs