EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 84

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Modes
4–10
Stratix III Device Handbook, Volume 1
1
Single Port RAM
All TriMatrix memory blocks support single-port mode. Single-port
mode allows you to do either one-read or one-write operation at a time.
Simultaneous reads and writes are not supported in single-port mode.
Figure 4–7
Figure 4–7. Single-Port Memory
Note to
(1)
During a write operation, behavior of the RAM outputs is configurable. If
you use the read-enable signal and perform a write operation with the
read enable deactivated, the RAM outputs retain the values they held
during the most recent active read enable. If you activate read enable
during a write operation, or if you are not using the read-enable signal at
all, the RAM outputs either show the new data being written, the old data
at that address, or a don't care value. To choose the desired behavior, set
the read-during-write behavior to either new data, old data, or don't care
in the RAM MegaWizard
Write” on page 4–21
You can implement two single-port memory blocks in a single M9K or M144K
block. See
Figure
When using the memory blocks in ROM, single-port, simple
dual-port, or true dual-port mode, you can corrupt the memory
contents if you violate the setup or hold-time on any of the
memory block input registers. This applies to both read and
write operations.
shows the single-port RAM configuration.
“Packed Mode Support” on page 4–5
4–7:
data[ ]
address[ ]
wren
byteena[]
addressstall
clockena
rden
aclr
for more details on this behavior.
inclock
®
in the Quartus II software. See
Note (1)
for more details.
outclock
q[]
Altera Corporation
November 2007
“Read During