EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 267

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–30. Single-Ended Row I/O Pin Placement with Respect to LVDS I/O Pins
Altera Corporation
November 2007
No single - ended input
with OCT R
T
The restriction on placing single-ended column I/O is similar to that on
row I/O. You should place the single-ended outputs with drive strength
equal to or greater than 8 mA at least four I/Os away from the LVDS I/O.
The same rule applies to single-ended input with OCT R
does not apply when the LVDS input buffer is used for differential
HSTL/SSTL inputs. Single-ended outputs with a driving strength less
than 8 mA and single-ended inputs without OCT R
The single-ended I/O placement rules for column I/O are shown in
Figure
7–31.
Row boundary
No single -ended outputs
equal to or greater than 8 mA
SE input without OCT R
SE output less than 8 mA or SE input without OCT R
LVDS I/O
SE output equal to or more than 8 mA or SE input with OCT R
Stratix III Device Handbook, Volume 1
T
Stratix III Device I/O Features
T
have no restriction.
T
. The restriction
T
T
7–49