EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 540

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–28
Stratix III Device Handbook, Volume 2
The timing numbers listed in the tables of this section are extracted from
the Quartus II software version 7.2.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Stratix III device timing models.
Preliminary status means that the timing models are subject to change in
future Quartus II releases. Initially, timing numbers are created using
simulation results, process data, and other known parameters. Parts of
the timing models may be correlated to silicon measurements. Various
tests are used to make the preliminary numbers as close to the actual
timing parameters as possible.
Final timing models are based on simulation models that are
characterized versus the actual device measurements under all allowable
operating conditions. When the timing models are final, all or most of the
Stratix III family devices have been completely characterized and no
further changes to the timing model are expected.
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (t
and hold time (t
to calculate t
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Table 1–34. Stratix III Device Timing Model Status
Device
SU
and t
H
). The Quartus II software uses the following equations
H
timing for Stratix III devices input signals.
Preliminary
Table 1–34
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v
v
shows the status of the
Altera Corporation
November 2007
Final
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SU
)