EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 630

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–118
Stratix III Device Handbook, Volume 2
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V
LVTTL
Standard
Table 1–63. EP3SL70 Column Pin Delay Adders for Regional Clock
Table 1–64. EP3SL70 Row Pin Delay Adders for Regional Clock
Table 1–65. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Parameter
Parameter
GCLK
GCLK
Clock
PLL
Parameter
t
t
t
t
SU
SU
H
H
Table 1–64
Regional Clock.
EP3SL110 I/O Timing Parameters
Table 1–65
parameters for EP3SL110 devices for single-ended I/O standards.
Table 1–65
single-ended I/O standards.
Industrial
Industrial
—
—
—
—
—
—
Industrial Commercial
—
—
—
—
Fast Model
Fast Model
Fast Model
specifies EP3SL110 Column Pins Input Timing parameters for
specifies EP3SL70 Row Pin delay adders when using the
through
Commercial
Commercial
-0.055
1.758
1.703
0.002
-0.928
-0.336
0.001
0.006
1.036
0.444
Table 1–69
-1.360 -1.452 -1.601 -1.542 -1.910
-0.696 -0.825 -0.960 -0.904 -0.816
V
1.502
0.838
1.1V
V
2.663
2.581
0.083
0.002
CCL
0.079
V
-2
1.1V
1.1V
0.08
show the maximum I/O timing
CCL
CCL
-2
-2
=
=
=
1.613
0.986
V
1.1V
V
2.985
2.779
0.153
0.078
CCL
1.1V
V
0.158
0.161
-3
1.1V
CCL
-3
CCL
-3
=
=
=
V
1.776
1.135
1.1V
V
3.268
3.037
0.107
0.158
1.1V
CCL
0.249
0.254
V
-4
1.1V
CCL
-4
CCL
-4
=
=
=
1.709
1.071
V
1.1V
V
3.053
2.971
0.076
0.111
1.1V
CCL
-4L
V
0.205
0.209
CCL
1.1V
CCL
Altera Corporation
=
=
-4L
=
-4L
November 2007
V
2.071
0.977
V
2.895
2.744
0.302
0.364
0.9V
0.9V
-4L
CCL
0.415
0.419
CCL
V
0.9V
CCL
=
=
=
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns