EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 451

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 13–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
Altera Corporation
November 2007
Capture Phase
In the capture phase, the
signals at the pin, OEJ and
OUTJ, are loaded into the
capture registers. The CLOCK
signals are supplied by the TAP
controller's CLOCKDR output.
The data retained in these
registers consists of signals
from normal device operation.
Shift & Update Phases
In the shift phase, the
previously captured signals at
the pin, OEJ and OUTJ, are
shifted out of the boundary-scan
register via the TDO pin using
CLOCK. As data is shifted out,
the patterns for the next test
can be shifted in via the
TDI pin.
In the update phase, data is
transferred from the capture
registers to the update
registers using the UPDATE
clock. The data stored in the
update registers can be used
for the EXTEST instruction.
OUTJ
OUTJ
OEJ
OEJ
SDI
SDI
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
0
1
0
1
0
1
0
1
0
1
0
1
SHIFT
SHIFT
CLOCK
CLOCK
Registers
D
D
D
Registers
Capture
D
D
D
Capture
Q
Q
Q
Q
Q
Q
SDO
SDO
UPDATE
UPDATE
Stratix III Device Handbook, Volume 1
Registers
D
D
D
Registers
D
D
D
Update
Update
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
0
1
0
1
0
1
MODE
MODE
PIN_IN
PIN_IN
INJ
INJ
13–13