EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 276

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Interfaces Pin Support
Memory
Interfaces Pin
Support
8–6
Stratix III Device Handbook, Volume 1
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS
and DQSn/CQn), address, command, and clock pins. Some memory
interfaces use data mask (DM) pins to enable write masking and QVLD
pins to indicate that the read data is ready to be captured. This section
describes how Stratix III devices support all these different pins.
Data and Data Clock/Strobe Pins
Stratix III DDR memory interface data pins are called DQ pins. The read
data-strobes or clocks are called DQS pins. Depending on the memory
specifications, the DQS pins can be bi-directional single-ended signals (in
DDR2 and DDR SDRAM), uni-directional differential signals (in
RLDRAM II), bi-directional differential signals (DDR3 and DDR2
SDRAM), or uni-directional complementary signals (QDRII+ and QDRII
SRAM). Connect the uni-directional read and write data-strobes or clocks
to Stratix III DQS pins.
Stratix III devices offer differential input buffers for differential read
data-strobe/clock operations and provide an independent DQS logic
block for each CQn pin for complementary read data-strobe/clock
operations. In the Stratix III pin tables, the differential DQS pin-pairs are
denoted as DQS and DQSn pins, while the complementary DQS signals
are denoted as DQS and CQn pins. DQSn and CQn pins are marked
separately in the pin table. Each CQn pin connects to a DQS logic block
and the shifted CQn signals go to the active-low input registers in the DQ
IOE registers.
1
The DQ pins can be bi-directional signals, as in DDR3, DDR2, and DDR
SDRAM, and RLDRAM II common I/O (CIO) interfaces, or uni-
directional signals, as in QDRII+, QDRII SRAM, and RLDRAM II
separate I/O (SIO) devices. Connect the uni-directional read data signals
to Stratix III DQ pins and the uni-directional write data signals to a
different group of Stratix III DQ pins.
1
In DDR2 SDRAM, you can use the optional differential
DQS/DQSn feature in Stratix III devices for better signal
integrity. You can also use the single-ended DQS option to
reduce pin use. Differential DQS signaling, however, is
recommended for DDR2 SDRAM interfaces running higher
than 333 MHz.
Using a DQS/DQ group for the write data signals minimizes
output skew, allows access to the write leveling circuitry (for
DDR3 SDRAM interfaces), and allows vertical migration. These
pins also have access to deskewing circuitry that can
compensate for delay mismatch between signals on the bus.
Altera Corporation
November 2007