EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 77

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Table 4–2. TriMatrix Memory Capacity and Distribution in Stratix III Devices
Device
MLABs
1,350
2,150
2,850
4,000
6,750
1,600
2,150
5,100
950
950
Table 4–2
blocks in each Stratix III family member
TriMatrix Memory Block Types
While the M9K and M144K memory blocks are dedicated resources, the
MLABs are dual-purpose blocks. They can be configured as regular logic
array blocks (LABs) or as memory logic array blocks (MLABs). Ten ALMs
make up one MLAB. Each ALM in an MLAB can be configured as either
a 64 × 1 or a 32 × 2 block, resulting in a 64 × 10 or 32 × 20 simple dual-port
SRAM block in a single MLAB.
Parity Bit Support
All TriMatrix memory blocks have built-in parity-bit support. The ninth
bit associated with each byte can store a parity bit or serve as an
additional data bit. No parity function is actually performed on the ninth
bit.
Byte Enable Support
All TriMatrix memory blocks support byte enables that mask the input
data so that only specific bytes of data are written. The unwritten bytes
retain the previous written value. The write enable (wren) signals, along
with the byte enable (byteena) signals, control the RAM blocks' write
operations.
M9K Blocks
1,040
108
150
275
355
468
400
495
639
864
shows the capacity and distribution of the TriMatrix memory
TriMatrix Embedded Memory Blocks in Stratix III Devices
M144K
Blocks
12
16
36
48
12
12
16
48
6
6
Bits (dedicated memory
Total Dedicated RAM
blocks only)
16,272 Kb
14,688 Kb
Stratix III Device Handbook, Volume 1
1,836 Kb
2,214 Kb
4,203 Kb
5,499 Kb
9,396 Kb
5,328 Kb
6,183 Kb
8,055 Kb
.
(including MLABs)
Total RAM Bits
11,896 Kb
20,491 Kb
17,876 Kb
2,430 Kb
3,058 Kb
5,547 Kb
7,280 Kb
5,922 Kb
7,183 Kb
9,399 Kb
4–3