EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 159
EP3SL150F780I3N
Manufacturer Part Number
EP3SL150F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheet
1.EP3SL110.pdf
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Altera Corporation
November 2007
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
Clock Resource
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
Clock Resources
Table 6–2. Clock Input Pin Connectivity to Global Clock Networks
Table 6–3. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 1) (Part 1 of 2)
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Table 6–2
and GCLKs.
Table 6–3
and RCLKs in device Quadrant 1. A given clock input pin can drive two
adjacent regional clock networks to create a dual-regional clock network.
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shows the connection between the dedicated clock input pins
shows the connectivity between the dedicated clock input pins
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CLK (p/n Pins)
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CLK (p/n Pins)
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Clock Networks and PLLs in Stratix III Devices
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Stratix III Device Handbook, Volume 1
9
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