EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 482

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Error Detection Block
Error Detection
Block
15–8
Stratix III Device Handbook, Volume 1
CRITICAL ERROR Pin
The CRC_ERROR pin information for Stratix III devices is reported in
Device Pin-Outs on the Literature page of the Altera website
(www.altera.com).
The CRITICAL ERROR pin information for Stratix III devices will be
included in Device Pin-Outs on the Literature page of the Altera website
(www.altera.com) in the later revision.
You can enable the Stratix III device error detection block in the
Quartus II software (refer to
block contains the logic necessary to calculate the 16-bit CRC signature
for the configuration CRAM bits in the device.
The CRC circuit continues running even if an error occurs. When a soft
error occurs, the device sets the CRC_ERROR pin high. Two types of CRC
detection checks the configuration bits:
■
CRITICAL ERROR
Table 15–4. CRITICAL ERROR Pin Description
The first type is the CRAM error checking ability (16-bit CRC) during
user mode, for use by the CRC_ERROR pin.
●
●
●
●
●
Pin Name
For each frame of data, the pre-calculated 16-bit CRC enters the
CRC circuit right at the end of the frame data and determines
whether there is an error or not.
If an error occurs, the search engine starts to find the location of
the error.
The error messages can be shifted out through the JTAG
instruction or core interface logics while the error detection
block continues running.
The JTAG interface reads out the 16-bit CRC result for the first
frame and also shifts the 16-bit CRC bits to the 16-bit CRC
storage registers for test purpose.
Single error, double errors, or double errors adjacent to each
other can be deliberately introduced to configuration memory
for testing and design verification.
Table 15–4
I/O, output
Pin Type
“Software Support” on page
describes the CRITICAL ERROR pin.
Active high signal that indicates that
the sensitivity processor reference
design has detected errors in the
configuration CRAM bits. This pin is
optional and is used when the critical
error detection is enabled.
Description
Altera Corporation
15–12). This
October 2007