EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 394

no-image

EP3SL150F780I3N

Manufacturer Part Number
EP3SL150F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F780I3N
Manufacturer:
PMI
Quantity:
4
Part Number:
EP3SL150F780I3N
Manufacturer:
AVX
Quantity:
2
Part Number:
EP3SL150F780I3N
Manufacturer:
ALTERA
Quantity:
546
Part Number:
EP3SL150F780I3N
Manufacturer:
XILINX
0
Part Number:
EP3SL150F780I3N
Manufacturer:
ALTERA
0
Part Number:
EP3SL150F780I3N
Manufacturer:
ALTERA
Quantity:
220
Part Number:
EP3SL150F780I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP3SL150F780I3N
Quantity:
280
Part Number:
EP3SL150F780I3N WWW.YIBEIIC.COM
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Passive Serial Configuration
11–34
Stratix III Device Handbook, Volume 1
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[0] pin is available as
a user I/O pin after configuration. When you chose the PS scheme as a
default in the Quartus II software, this I/O pin is tri-stated in user mode
and should be driven by the MAX II device. To change this default option
in the Quartus II software, select the Dual-Purpose Pins tab of the Device
and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device and Pin Options dialog box) is turned
on, the Stratix III device releases nSTATUS after a reset time-out period
(maximum of 100 ms). After nSTATUS is released and pulled high by a
pull-up resistor, the MAX II device can try to reconfigure the target
device without needing to pulse nCONFIG low. If this option is turned off,
the MAX II device must generate a low-to-high transition (with a low
pulse of at least 2ms) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but CONF_DONE
or INIT_DONE have not gone high, the MAX II device must reconfigure
the target device.
1
When the device is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 2 ms. When nCONFIG is pulled low, the device also pulls
If you use the optional CLKUSR pin and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 100 ms).
Altera Corporation
November 2007

Related parts for EP3SL150F780I3N