EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 460

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1 BST Guidelines
IEEE Std. 1149.1
BST Guidelines
13–22
Stratix III Device Handbook, Volume 1
Table 13–7
Std. 1149.1 circuitry in Stratix III devices.
Use the following guidelines when performing boundary-scan testing
with IEEE Std. 1149.1 devices:
■
w
Note to
(1)
TMS
TCK
TDI
TDO
TRST
Table 13–7. Disabling IEEE Std. 1149.1 Circuitry
If the “10...” pattern does not shift out of the instruction register via
the TDO pin during the first clock cycle of the SHIFT_IR state, the
TAP controller did not reach the proper state. To solve this problem,
try one of the following procedures:
●
●
There is no software option to disable JTAG in Stratix III devices.
The JTAG pins are dedicated.
JTAG Pins
Table
Verify that the TAP controller has reached the SHIFT_IR state
correctly. To advance the TAP controller to the SHIFT_IR state,
return to the RESET state and send the code 01100 to the TMS
pin.
Check the connections to the V
configuration pins on the device.
Do NOT use the following private instructions as they may
render the device inoperable:
11 0001 0000
00 1100 1001
11 0001 0011
11 0001 0111
You should take precautions not to invoke these instructions at
any time.
shows the pin connections necessary for disabling the IEEE
13–7:
(1)
V
GND
V
Leave open
GND
CCPD
CCPD
Connection for Disabling
supply of Bank 1A
supply of Bank 1A
CC
, GND, JTAG, and dedicated
Altera Corporation
November 2007