EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 67

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 3–5. M9K RAM Block LAB Row Interface
Altera Corporation
October 2007
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnects
M9K Local
Interconnect
20
20
The M9K RAM block local interconnect is driven by the R4, C4, and direct
link interconnects from adjacent LABs. The M9K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
resources. Up to 20 direct link input connections to the M9K RAM Block
are possible from the left adjacent LABs and another 20 possible from the
right adjacent LAB. M9K RAM block outputs can also connect to left and
right LABs through direct link interconnect.
RAM block to logic array interface.
The M144K blocks use eight interfaces in the same device column. The
M144K block local interconnects are driven by R4, C4, and direct link
interconnects from adjacent LABs on either the right or left side of the
MRAM block. Up to 20 direct link input connections to the M144K block
are possible from the left adjacent LABs and another 20 possible from the
right adjacent LAB. M144K block outputs can also connect to the LABs on
the block’s left and right sides through direct link interconnect.
shows the interface between the M144K RAM block and the logic array.
datain
control
signals
clocks
LAB Row Clocks
address
M9K
dataout
byte
enable
MultiTrack Interconnect in Stratix III Devices
36
Stratix III Device Handbook, Volume 1
20
Figure 3–5
shows the M9K
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnects
Figure 3–6
3–9