AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 170

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

18.3
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
32015G–AVR32–09/09
Block Diagram
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Peripherals
Figure 18-1. DMA Controller (DMACA) Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.
The user must first program the GPIO controller to assign the DMACA pins to their peripheral
functions.
To prevent bus errors the DMACA operation must be terminated before entering sleep mode.
The CLK_DMACA to the DMACA is generated by the Power Manager (PM). Before using the
DMACA, the user must ensure that the DMACA clock is enabled in the power manager.
The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the
DMACA interrupt requires programming the interrupt controller before configuring the DMACA.
Both the source peripheral and the destination peripheral must be set up correctly prior to the
DMA transfer.
HSB Master
HSB Slave
HSB Master
HSB Slave
I/F
I/F
DMA Controller
CFG
SRC
FSM
Channel 0
FIFO
Channel 1
FSM
DST
Generator
Interrupt
AT32AP7001
irq_dma
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