AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 658

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32.7.20
Name:
Access Type:
• EPT_ENABL: Endpoint Enable
0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a
hardware or USBA bus reset and participate in the device configuration.
1 = If set, the endpoint is enabled according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
• INTDIS_DMA: Interrupt Disables DMA
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the IEN regis-
ter EPT_INT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if
transfer completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally
completed, but the new DMA packet transfer is not started (not requested).
If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, ERR_FL_ISO...), then the
request cancellation may happen at any time and may immediately stop the current DMA transfer.
32015G–AVR32–09/09
SHRT_PCKT
MDATA_RX
NAK_OUT
For IN Transfer:
If this bit is set, then the EPTSTAx register TX_PK_RDY bit is set automatically when the current bank is full and at the
end of DMA buffer if the DMACONTROLx register END_B_EN bit is set.
The user may still set the EPTSTAx register TX_PK_RDY bit if the current bank is not full, unless the user wants to send
a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, then the EPTSTAx register RX_BK_RDY bit is automatically reset for the current bank when the last
packet byte has been read from the bank FIFO or at the end of DMA buffer if the DMACONTROLx register END_B_EN
bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached.
The user may still clear the EPTSTAx register RX_BK_RDY bit, for example, after completing a DMA buffer by software
if DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s).
31
23
15
–
7
USBA Endpoint Control Register
ERR_FLUSH
DATAX_RX
NAK_IN/
30
22
14
–
–
6
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
29
21
13
–
–
5
–
Read-only
EPTCTLx
ERR_FL_ISO
RX_SETUP/
NYET_DIS
28
20
12
–
–
4
TX_PK_RDY/
ERR_TRANS
INTDIS_DMA
27
19
11
–
–
3
BUSY_BANK
TX_COMPLT
26
18
10
–
2
–
AUTO_VALID
RX_BK_RDY
AT32AP7001
25
17
–
–
9
1
ERR_OVFLW
EPT_ENABL
24
16
–
–
8
0
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