AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 339

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

23.5.4
23.6
32015G–AVR32–09/09
Offset
0x00C
0x01C
0x10C
0x11C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
User Interface
Interrupts
PS/2 Transmit Holding Register 0
PS/2 Transmit Holding Register 1
PS/2 Interrupt Disable Register 0
PS/2 Interrupt Disable Register 1
PS/2 Receive Holding Register 0
PS/2 Receive Holding Register 1
PS/2 Interrupt Enable Register 0
PS/2 Interrupt Enable Register 1
When the data written to THR has been transmitted to the device, the TXRDY bit in SR will be
set and a new value can be loaded into THR.
At the end of the transfer, the device should acknowledge the transfer by pulling the data line
low for one cycle. If an acknowledge is not detected, the NACK bit in SR will be set.
If the device fails to acknowledge the frame, the NACK bit in SR will be set. The software is
responsible for any retries.
All transfers from host to device are started by the host pulling the clock line low for at least
100µs. The programmer must ensure that the prescaler is programmed to generate correct
pulse length.
The PS/2 module can be configured to signal an interrupt when one of the bits in SR is set. The
interrupt is enabled by writing to IER (Interrupt Enable Register) and disabled by writing to IDR
(Interrupt Disable Register). The current setting of an interrupt line can be seen by reading IMR
(Interrupt Mask Register).
PS/2 Interrupt Mask Register 0
PS/2 Interrupt Mask Register 1
PS/2 Prescale Register 0
PS/2 Prescale Register 1
PS/2 Control Register 0
PS/2 Control Register 1
PS/2 Status Register 0
PS/2 Status Register 1
RESERVED
RESERVED
RESERVED
RESERVED
Register
Register Name
RHR0
RHR1
THR0
PSR0
THR1
PSR1
IMR0
IMR1
IER0
IDR0
IER1
IDR1
CR0
SR0
CR1
SR1
-
-
-
-
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
-
-
-
-
AT32AP7001
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
-
339