AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 306

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

21.8.2
Name:
Access Type:
•
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
•
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
•
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
•
0 = The SPI operates at MCK.
1 = The SPI operates at MCK/N.
•
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
•
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in Master Mode only. MISO is internally connected to
MOSI.
32015G–AVR32–09/09
MSTR: Master/Slave Mode
PS: Peripheral Select
PCSDEC: Chip Select Decode
FDIV: Clock Selection
MODFDIS: Mode Fault Detection
LLB: Local Loopback Enable
LLB
CSR0 defines peripheral chip select signals 0 to 3.
CSR1 defines peripheral chip select signals 4 to 7.
CSR2 defines peripheral chip select signals 8 to 11.
CSR3 defines peripheral chip select signals 12 to 14.
31
23
15
–
–
7
SPI Mode Register
30
22
14
–
–
6
–
29
21
13
–
–
5
–
MR
Read/Write
MODFDIS
28
20
12
–
–
4
DLYBCS
FDIV
27
19
11
–
3
PCSDEC
26
18
10
–
2
PCS
AT32AP7001
PS
25
17
–
9
1
MSTR
24
16
–
8
0
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