AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 743

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Table 35-3.
Table 35-4.
Table 35-5.
35.5.3
32015G–AVR32–09/09
RGB 5:6:5
Mode
RGB 5:6:5
Mode
RGB 8:8:8
RGB 5:6:5
Clocks
RGB Format in Default Mode, RGB_CFG = 00, No Swap
RGB Format, RGB_CFG = 10 (Mode 2), No Swap
RGB Format in Default Mode, RGB_CFG = 00, Swap Activated
Byte 0
Byte 1
Byte 2
Byte 3
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
The RGB 5:6:5 input format is processed to be displayed as RGB 5:5:5 format.
The sensor master clock (MCK) can be generated either by the power manager through a pro-
grammable clock output or by an external oscillator connected to the sensor.
None of the sensors embeds a power management controller, so providing the clock by the
power manager is a simple and efficient way to control power consumption of the system.
Care must be taken when programming the system clock. The ISI has two clock domains, the
system bus clock and the pixel clock provided by sensor. The two clock domains are not syn-
chronized, but the system clock must be faster than pixel clock.
R4(i)
G2(i)
R4(i+1)
G2(i+1)
D7
G2(i)
B4(i)
G2(i+1)
B4(i+1)
D7
R0(i)
G0(i)
B0(i)
R0(i+1)
G3(i)
B0(i)
G3(i+1)
B0(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
D6
G1(i)
B3(i)
G1(i+1)
B3(i+1)
D6
R1(i)
G1(i)
B1(i)
R1(i+1)
G4(i)
B1(i)
G4(i+1)
B1(i+1)
R2(i)
G0(i)
R2(i+1)
G0(i+1)
D5
G0(i)
B2(i)
G0(i+1)
B2(i+1)
D5
R2(i)
G2(i)
B2(i)
R2(i+1)
G5(i)
B2(i)
G5(i+1)
B2(i+1)
R1(i)
B4(i)
R1(i+1)
B4(i+1)
D4
R4(i)
R4(i+1)
B1(i+1)
D4
R3(i)
G3(i)
R3(i+1)
R0(i)
R0(i+1)
B3(i+1)
B1(i)
B3(i)
B3(i)
R0(i)
B3(i)
R0(i+1)
B3i+1)
D3
R3(i)
B0(i)
R3(i+1)
B0(i+1)
D3
R4(i)
G4(i)
B4(i)
R4(i+1)
R1(i)
B4(i)
R1(i+1)
B4(i+1)
G5(i)
R5(i)
B5(i)
G0(i)
G5(i)
B2(i)
G5(i+1)
B2(i+1)
D2
R2(i)
R2(i+1)
G5(i+1)
D2
G5(i)
R5(i+1)
R2(i)
R2(i+1)
G0(i+1)
AT32AP7001
G4(i)
B1(i)
G4(i+1)
B1(i+1)
D1
R1(i)
G4(i)
R1(i+1)
G4(i+1)
D1
R6(i)
G6(i)
B6(i)
R6(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
R0(i)
R0(i+1)
R7(i)
R7(i+1)
R4(i)
R4(i+1)
G3(i)
B0(i)
G3(i+1)
B0(i+1)
D0
G3(i)
G3(i+1)
D0
G7(i)
B7(i)
G2(i)
G2(i+1)
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