AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 181

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

18.9.1.4
18.9.2
32015G–AVR32–09/09
Ending Multi-block Transfers
Suspension of Transfers Between Blocks
blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and
CFGx.RELOAD_DS registers (see
Note:
At the end of every block transfer, an end of block interrupt is asserted if:
• interrupts are enabled, CTLx.INT_EN = 1
• the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.
Note:
For rows 6, 8, and 10 of
transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1.
For rows 2, 3, 4, 7, and 9 of
block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted
if the end of block interrupt is enabled and unmasked.
The DMACA does not proceed to the next block transfer until a write to the block interrupt clear
register, ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.
For rows 2, 3, 4, 7, and 9 of
block transfers), the DMA transfer does not stall if either:
• interrupts are disabled, CTLx.INT_EN = 0, or
• the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.
Channel suspension between blocks is used to ensure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits
b efo re co mp let ion of t he fina l blo ck. Th e r elo ad bit s CFGx .REL OAD _SR a nd /o r
CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block
transfer.
All multi-block transfers must end as shown in either Row 1 or Row 5 of
At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in
Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA trans-
fer is terminated.
Note:
For rows 2,3 and 4 of
C F G x . R E L O A D _ D S i s s e t ) , m u l t i - b l o c k D M A t r a n s f e r s c o n t i n u e u n t i l b o t h t h e
CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be
Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is
required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max-
imum value, use Row 10 of
block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the
LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous
block.
The block complete interrupt is generated at the completion of the block transfer to the destination.
Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in
Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for
the last block.
Table 18-1 on page
Table 18-1 on page
Table 18-1 on page 180
Table 18-1 on page 180
Table 18-1 on page 180
Figure 18-1 on page
180, the DMA transfer does not stall between block
180, (LLPx = 0 and CFGx.RELOAD_SR and/or
(SARx and/or DARx auto-reloaded between
(SARx and/or DARx auto-reloaded between
170).
and setup the LLI.SARx address of the
AT32AP7001
Table 18-1 on page
180.
181