AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 101

• Manufacturer Part Number: AT91SAM7X256B-CU
• Description: IC MCU 256KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: 91S
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, Ethernet, SPI, I2S, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• On-chip Adc: 8-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

AT91SAM7X512/256/128 Preliminary
• MST_PDC: PDC Abort Source
0: The last aborted access was not due to the PDC.
1: The last aborted access was due to the PDC.
• MST_ARM: ARM Abort Source
0: The last aborted access was not due to the ARM.
1: The last aborted access was due to the ARM.
• SVMST_EMAC: Saved EMAC Abort Source
0: No abort due to the EMAC occurred since the last read of MC_ASR or it is notified in the bit MST_EMAC.
1: At least one abort due to the EMAC occurred since the last read of MC_ASR.
• SVMST_PDC: Saved PDC Abort Source
0: No abort due to the PDC occurred since the last read of MC_ASR or it is notified in the bit MST_PDC.
1: At least one abort due to the PDC occurred since the last read of MC_ASR.
• SVMST_ARM: Saved ARM Abort Source
0: No abort due to the ARM occurred since the last read of MC_ASR or it is notified in the bit MST_ARM.
1: At least one abort due to the ARM occurred since the last read of MC_ASR.
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