AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 284

• Manufacturer Part Number: AT91SAM7X256B-CU
• Description: IC MCU 256KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: 91S
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, Ethernet, SPI, I2S, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• On-chip Adc: 8-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 29-6. Master Write with Multiple Data Byte
Figure 29-7. Master Write with One Byte Internal Address and Multiple Data Bytes
284
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
AT91SAM7X512/256/128 Preliminary
Write THR (Data n)
S
Write THR (Data n)
S
DADR
DADR
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in
the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR. When no more data is written
into the TWI_THR, the master generates a stop condition to end the transfer. The end of the
complete transfer is marked by the TWI_TXCOMP bit set to one. See
and
Figure 29-5. Master Write with One Data Byte
W
Figure
W
TXCOMP
A
TXRDY
TWD
29-7.
IADR(7:0)
A
Write THR (DATA)
S
Write THR (Data n+1)
DATA n
A
DADR
DATA n
Write THR (Data n+1)
A
W
A
A
Write THR (Data n+x)
DATA n+5
Last data sent
DATA
Write THR (Data n+x)
DATA n+5
Last data sent
A
(ACK received and TXRDY = 1)
A
DATA n+x
A
STOP sent automaticaly
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
P
STOP sent automaticaly
Figure
DATA n+x
STOP sent automaticaly
6120H–ATARM–17-Feb-09
29-5,
A
A
Figure
P
P
29-6,