AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 269

• Manufacturer Part Number: AT91SAM7X256B-CU
• Description: IC MCU 256KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: 91S
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, Ethernet, SPI, I2S, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• On-chip Adc: 8-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.7.2
Name:
Access Type:
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on
MOSI.)
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
6120H–ATARM–17-Feb-09
LLB
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
31
23
15
–
–
7
SPI Mode Register
SPI_MR
Read-write
30
22
14
–
–
6
–
29
21
13
–
–
5
–
MODFDIS
AT91SAM7X512/256/128 Preliminary
28
20
12
–
–
4
DLYBCS
27
19
11
–
3
PCSDEC
26
18
10
–
2
PCS
PS
25
17
–
9
1
MSTR
24
16
–
8
0
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