AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 232
![IC MCU 256KB FLASH 100TFBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
AT91SAM7X256B-CU
Manufacturer Part Number
AT91SAM7X256B-CU
Description
IC MCU 256KB FLASH 100TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X256B-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
91S
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, Ethernet, SPI, I2S, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
62
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Package
100TFBGA
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
On-chip Adc
8-chx10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
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27.4
Figure 27-3. I/O Line Control Logic
232
Output Enable
Output Enable
Peripheral A
Peripheral B
Functional Description
Peripheral A
Peripheral B
PIO_BSR[0]
PIO_ASR[0]
AT91SAM7X512/256/128 Preliminary
Output
Output
PIO_ABSR[0]
PIO_OER[0]
PIO_ODR[0]
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic asso-
ciated to each I/O is represented in
represents but one of up to 32 possible indexes.
1
1
0
0
PIO_OSR[0]
PIO_IFER[0]
PIO_IFDR[0]
PIO_SODR[0]
PIO_CODR[0]
PIO_IFSR[0]
PIO_PER[0]
PIO_PDR[0]
Glitch
Filter
PIO_ODSR[0]
PIO_PSR[0]
PIO_PDSR[0]
1
0
PIO_IER[31]
PIO_IDR[31]
PIO_IER[0]
PIO_IDR[0]
1
0
1
0
Detector
Edge
PIO_IMR[31]
PIO_ISR[31]
PIO_IMR[0]
PIO_ISR[0]
PIO_MDER[0]
PIO_MDDR[0]
Figure
PIO_MDSR[0]
27-3. In this description each signal shown
(Up to 32 possible inputs)
1
0
0
1
PIO_PUER[0]
PIO_PUDR[0]
PIO_PUSR[0]
PIO Interrupt
Peripheral B
Peripheral A
Input
Input
6120H–ATARM–17-Feb-09
Pad
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