AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 71

IC MCU 256KB FLASH 100TFBGA

AT91SAM7X256B-CU

Manufacturer Part Number
AT91SAM7X256B-CU
Description
IC MCU 256KB FLASH 100TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7X256B-CU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
91S
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, Ethernet, SPI, I2S, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
62
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Package
100TFBGA
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
On-chip Adc
8-chx10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X256B-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X256B-CU-999
Manufacturer:
Atmel
Quantity:
10 000
13.3.3
Register Name:
Access Type:
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• BODIEN: Brownout Detection Interrupt Enable
0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2
allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
6120H–ATARM–17-Feb-09
31
23
15
7
Reset Controller Mode Register
30
22
14
RSTC_MR
Read-write
6
29
21
13
5
URSTIEN
AT91SAM7X512/256/128 Preliminary
28
20
12
4
KEY
27
19
11
3
26
18
10
2
ERSTL
(ERSTL+1)
25
17
9
1
Slow Clock cycles. This
URSTEN
BODIEN
24
16
8
0
71

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