AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 47

• Manufacturer Part Number: AT91SAM7X256B-CU
• Description: IC MCU 256KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: 91S
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, Ethernet, SPI, I2S, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• On-chip Adc: 8-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3.2
12.4
6120H–ATARM–17-Feb-09
Debug and Test Pin Description
Test Environment
Figure 12-3
ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices.
These devices can be connected to form a single scan chain.
Figure 12-3. Application Test Environment Example
Table 12-1.
Pin Name
NRST
TST
TCK
TDI
TDO
TMS
JTAGSEL
DRXD
DTXD
shows a test environment example. Test vectors are sent and interpreted by the tes-
Debug and Test Pin List
AT91SAM7Xxx-based Application Board In Test
AT91SAM7X512/256/128 Preliminary
Connector
ICE/JTAG
AT91SAM7Xxx
Interface
JTAG
Function
Microcontroller Reset
Test Mode Select
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Debug Receive Data
Debug Transmit Data
Chip n
ICE and JTAG
Test Adaptor
Debug Unit
Reset/Test
Chip 2
Chip 1
Tester
Input/Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Active Level
High
Low
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