AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 444

• Manufacturer Part Number: AT91SAM7X256B-CU
• Description: IC MCU 256KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: 91S
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, Ethernet, SPI, I2S, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• On-chip Adc: 8-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

33.6.11
Register Name:PWM_CPRD[0. X-1]
Access Type: Read-write
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
444
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31
23
15
7
256, 512, or 1024). The resulting period formula will be:
256, 512, or 1024). The resulting period formula will be:
(
------------------------------- -
(
------------------------------------------ -
(
------------------------------------------ -
(
----------------------------------------------------- -
X
CRPD
2
2
AT91SAM7X512/256/128 Preliminary
×
×
PWM Channel Period Register
×
MCK
CPRD
X
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
)
×
DIVA
30
22
14
)
)
6
or
)
(
---------------------------------------------- -
or
CRPD
(
----------------------------------------------------- -
2
MCK
×
×
CPRD
DIVAB
29
21
13
MCK
5
×
)
DIVB
)
28
20
12
4
CPRD
CPRD
CPRD
CPRD
27
19
11
3
26
18
10
2
25
17
9
1
6120H–ATARM–17-Feb-09
24
16
8
0