LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 212
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
92
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
4. Features
UM10237_4
User manual
Table 181. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation
AHB
CRC
DMA
Double-word
FCS
Fragment
Frame
Half-word
LAN
MAC
MII
MIIM
Octet
Packet
PHY
RMII
Rx
TCP/IP
Tx
VLAN
WoL
Word
•
•
Ethernet standards support:
– Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
– Flexible transmit and receive frame options.
– VLAN frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
100 Base-FX, and 100 Base-T4.
pressure.
Definition
Advanced High-performance bus
Cyclic Redundancy Check
Direct Memory Access
64 bit entity
Frame Check Sequence (CRC)
A (part of an) Ethernet frame; one or multiple fragments can add up to a single
Ethernet frame.
An Ethernet frame consists of destination address, source address, length
type field, payload and frame check sequence.
16 bit entity
Local Area Network
Media Access Control sublayer
Media Independent Interface
MII management
An 8 bit data entity, used in lieu of "byte" by IEEE 802.3
A frame that is transported across Ethernet; a packet consists of a preamble,
a start of frame delimiter and an Ethernet frame.
Ethernet Physical Layer
Reduced MII
Receive
Transmission Control Protocol / Internet Protocol. The most common
high-level protocol used with Ethernet.
Transmit
Virtual LAN
Wake-up on LAN
32 bit entity
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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