LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 5
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Part Number:
LPC2470FET208,551
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Part Number:
LPC2470FET208,551
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UM10237_4
User manual
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– SPI controller.
– Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
– Three I
– I
Other peripherals:
– SD/MMC memory card interface.
– 160 general purpose I/O pins with configurable pull-up/down resistors.
– 10-bit ADC with input multiplexing among 8 pins.
– 10-bit DAC.
– Four general purpose timers/counters with 8 capture inputs and 10 compare
– Two PWM/timer blocks with support for three-phase motor control. Each PWM has
– Real-Time Clock (RTC) with separate power domain, clock source can be the RTC
– 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
– WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
Each peripheral has its own clock divider for further power saving. These dividers help
reducing active power by 20 - 30 %.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip power-on reset.
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA
controller.
the GPDMA.
outputs. Each timer block has an external count input.
an external count inputs.
oscillator or the APB clock.
rest of the chip is powered off.
the RTC oscillator, or the APB clock.
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
2
C-bus interfaces (one with open-drain and two with standard port pins).
Rev. 04 — 26 August 2009
Chapter 1: LPC24XX Introductory information
UM10237
© NXP B.V. 2009. All rights reserved.
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