LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 554
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
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Part Number:
LPC2470FET208,551
Manufacturer:
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UM10237_4
User manual
5.3.1 Adapter register block
5.3.2 Control unit
5.3.3 Command path
5.3.4 Command path state machine
The adapter register block contains all system registers. This block also generates the
signals that clear the static flags in the multimedia card. The clear signals are generated
when 1 is written into the corresponding bit location of the MCIClear register.
The control unit contains the power management functions and the clock divider for the
memory card clock.
There are three power phases:
The power management logic controls an external power supply unit, and disables the
card bus output signals during the power-off or power-up phases. The power-up phase is
a transition phase between the power-off and power-on phases, and allows an external
power supply to reach the card bus operating voltage. A device driver is used to ensure
that the PrimeCell MCI remains in the power-up phase until the external power supply
reaches the operating voltage.
The clock management logic generates and controls the MCICLK signal. The MCICLK
output can use either a clock divide or clock bypass mode. The clock output is inactive:
The command path subunit sends commands to and receives responses from the cards.
When the command register is written to and the enable bit is set, command transfer
starts. When the command has been sent, the Command Path State Machine (CPSM)
sets the status flags and enters the IDLE state if a response is not required. If a response
is required, it waits for the response (see
the received CRC code and the internally generated code are compared, and the
appropriate status flags are set.
•
•
•
•
•
•
Power-off
Power-up
Power-on
after reset
during the power-off or power-up phases
if the power saving mode is enabled and the card bus is in the IDLE state (eight clock
periods after both the command and data path subunits enter the IDLE phase)
Rev. 04 — 26 August 2009
Figure
Chapter 21: LPC24XX SD/MMC card interface
21–107). When the response is received,
UM10237
© NXP B.V. 2009. All rights reserved.
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