LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 344
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Quantity
Price
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Part Number:
LPC2470FET208,551
Manufacturer:
Exar
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Part Number:
LPC2470FET208,551
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Table 308. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit description
UM10237_4
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
EP0RX
EP0TX
EP1RX
EP1TX
EP2RX
EP2TX
EP3RX
EP3TX
EP4RX
EP4TX
EP5RX
EP5TX
EP6RX
EP6TX
EP7RX
EP7TX
EP8RX
EP8TX
EP9RX
EP9TX
EP10RX
EP10TX
EP11RX
EP11TX
EP12RX
EP12TX
EP13RX
EP13TX
EP14RX
EP14TX
EP15RX
EP15TX
9.4.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0xFFE0 C234)
Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 2, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 3, Isochronous endpoint.
Endpoint 4, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 5, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 6, Isochronous endpoint.
Endpoint 7, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 8, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 9, Isochronous endpoint.
Endpoint 10, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 11, Data Received Interrupt bit.
Endpoint 11, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 12, Isochronous endpoint.
Endpoint 13, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 14, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 15, Data Transmitted Interrupt bit or sent a NAK.
Description
Endpoint 0, Data Received Interrupt bit.
Endpoint 1, Data Received Interrupt bit.
Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 2, Data Received Interrupt bit.
Endpoint 3, Isochronous endpoint.
Endpoint 4, Data Received Interrupt bit.
Endpoint 5, Data Received Interrupt bit.
Endpoint 6, Isochronous endpoint.
Endpoint 7, Data Received Interrupt bit.
Endpoint 8, Data Received Interrupt bit.
Endpoint 9, Isochronous endpoint.
Endpoint 10, Data Received Interrupt bit.
Endpoint 12, Isochronous endpoint.
Endpoint 13, Data Received Interrupt bit.
Endpoint 14, Data Received Interrupt bit.
Endpoint 15, Data Received Interrupt bit.
Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set
when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the
corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated
endpoint. USBEpIntEn is a read/write register.
Rev. 04 — 26 August 2009
Chapter 13: LPC24XX USB device controller
UM10237
© NXP B.V. 2009. All rights reserved.
Reset value
0
0
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
NA
NA
0
0
0
0
0
0
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