LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 616
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
92
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
5.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)
5.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)
5.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)
Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in
chapter for details of DMA operation.
Table 537: DMA Configuration register 1 (I2SDMA1 - address 0xE008 8014) bit description
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in
Table 538: DMA Configuration register 2 (I2SDMA2 - address 0xE008 8018) bit description
The I2SIRQ register controls the operation of the I
in I2SIRQ are shown in
Bit
15:8
23:16 tx_level
31:24 -
Bit
0
1
7:2
15:8
23:16
31:24
Bit
0
1
7:2
15:8
23:16
31:24
Symbol
rx_level
Symbol
rx_dma2_enable
tx_dma2_enable
Unused
rx_depth_dma2
tx_depth_dma2
-
Symbol
rx_dma1_enable
tx_dma1_enable
Unused
rx_depth_dma1
tx_depth_dma1
-
Description
Reflects the current level of the Receive FIFO.
Reflects the current level of the Transmit FIFO.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Table
Table
Table
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request on
DMA1.
Set the FIFO level that triggers a transmit DMA request on
DMA1.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request
on DMA2.
Set the FIFO level that triggers a transmit DMA request
on DMA2.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
23–537. Refer to the General Purpose DMA Controller
23–532.
23–532.
2
S interrupt request. The function of bits
Chapter 23: LPC24XX I
2
2
S receive.
S transmit.
2
2
S receive.
S transmit.
UM10237
© NXP B.V. 2009. All rights reserved.
2
S interface
Reset
Value
0
0
0
0
0
NA
616 of 792
0
0
Reset
Value
NA
Reset
Value
0
0
0
0
0
NA
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