LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 486

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
Table 425. Bus Timing Register (CAN1BTR - address 0xE004 4014, CAN2BTR - address
Baud rate prescaler
The period of the CAN system clock t
bit timing. The CAN system clock t
Synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, any
bus controller must re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width t
cycles a certain bit period may be shortened or lengthened by one re-synchronization:
Time segment 1 and time segment 2
Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period
and the location of the sample point:
Bit
9:0
13:10 -
15:14 SJW
19:16 TESG1
22:20 TESG2
23
31:24 -
Symbol Value Function
BRP
SAM
0xE004 8014) bit description
0
1
Rev. 04 — 26 August 2009
The Synchronization Jump Width is (this value plus one)
Sampling
The bus is sampled once (recommended for high speed
buses)
The bus is sampled 3 times (recommended for low to
medium speed buses to filter spikes on the bus-line)
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Baud Rate Prescaler. The APB clock is divided by (this
value plus one) to produce the CAN clock.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
CAN clocks.
The delay from the nominal Sync point to the sample point
is (this value plus one) CAN clocks.
The delay from the sample point to the next nominal sync
point is (this value plus one) CAN clocks. The nominal CAN
bit time is (this value plus the value in TSEG1 plus 3) CAN
clocks.
t
SCL
t
SCL
SJW
t
SYNCSEG
SCL
=
is calculated using the following equation:
=
Chapter 18: LPC24XX CAN controllers CAN1/2
t
CANsuppliedCLK
is programmable and determines the individual
t
SCL
×
=
SJW
(
t
SJW
SCL
defines the maximum number of clock
+
×
1
(
)
BRP
+
1
)
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
NA
0
1100
001
0
NA
486 of 792
RM
Set
X
X
X
X
X
(6)
(7)
(8)