LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 287

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
Fig 36. LCD controller block diagram
6.1.1 AMBA AHB slave interface
6.1 AHB interfaces
interface
interface
master
slave
AHB
AHB
There is also a single combined interrupt that is asserted when any of the individual
interrupts become active.
Figure 12–36
The LCD controller includes two separate AHB interfaces. The first, an AHB slave
interface, is used primarily by the CPU to access control and data registers within the LCD
controller. The second, an AHB master interface, is used by the LCD controller for DMA
access to display data stored in memory elsewhere in the system. The LCD DMA
controller can only access the 10 kB SRAM on AHB1 and the external memory.
The AHB slave interface connects the LCD controller to the AHB bus and provides CPU
accesses to the registers and palette RAM.
•
Bus error.
control
Lower
Upper
panel
panel
FIFO
FIFO
FIFO
Input
DMA
DMA
shows a simplified block diagram of the LCD controller.
serializer
Pixel
Rev. 04 — 26 August 2009
Hardware
(128x32)
palette
Cursor
RAM
FIFO underflow
AHB error
scaler
Gray
Chapter 12: LPC24XX LCD controller
formatter
formatter
Upper
Lower
panel
panel
Panel clock
generator
controller
Timing
generation
STN/TFT
Interrupt
select
data
Upper
output
Lower
output
panel
panel
FIFO
FIFO
UM10237
LCD control
LCDCLKIN
LCD panel
© NXP B.V. 2009. All rights reserved.
LCD panel
signals
Interrupt
clock
Upper
Lower
STN
STN
data
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