LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 410

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
7.15 I2C Clock Low Register (I2C_CLKLO - 0xFFE0 C310)
7.16 Interrupt handling
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
low period of the slower I
Table 375. I2C_CLKLO register (I2C_CLKLO - address 0xFFE0 C310) bit description
The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All
OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt
register.
I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL,
to the USB_I2C_INT bit.
For more details on the interrupts created by device controller, see the USB device
chapter. For interrupts created by the host controllers, see the OHCI specification.
The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB
related interrupts to the VIC controller (see
Remark: During the HNP switching between host and device with the OTG stack active,
an action may raise several levels of interrupts. It is advised to let the OTG stack initiate
any actions based on interrupts and ignore device and host level interrupts. This means
that during HNP switching, the OTG stack provides the communication to the host and
device controllers.
Bit
7:0
Fig 58. USB OTG interrupt handling
Symbol
CDLO
HNP_SUCCESS
HNP_FAILURE
INTERRUPTS
INTERRUPTS
INTERRUPTS
USB DEVICE
REMOVE_PU
USB HOST
USB I2C
OTGIntSt
TMR
Rev. 04 — 26 August 2009
2
C serial clock, SCL.
Description
Clock divisor low. This value is the number of 48 MHz
clocks the serial clock (SCL) will be low.
USB_INT_REQ_DMA
USB_NEED_CLOCK
USB_INT_REQ_HP
USB_INT_REQ_LP
USB_HOST_INT
EN_USB_INTS
USB_OTG_INT
USB_I2C_INT
USBIntSt
Figure
Chapter 15: LPC24XX USB OTG controller
15–58).
UM10237
© NXP B.V. 2009. All rights reserved.
to VIC
channel #22
410 of 792
Reset
Value
0xB9