LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 573

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
Each of the three I
modes: master transmitter mode, master receiver mode, slave transmitter mode and
slave receiver mode.
The three I
with entire I
without causing a problem with other devices on the same I
specification" description under the heading "Fast-Mode", and notes for the table titled
"Characteristics of the SDA and SCL I/O stages for F/S-mode I
sometimes a useful capability, but intrinsically limits alternate uses for the same pins if the
I2C interface is not used. Seldom is this capability needed on multiple I2C interfaces
within the same microcontroller. Therefore, I
standard port pins, and do not support the ability to turn power off to the LPC2400 while
leaving the I
considered during system design while assigning uses for the I
Fig 111. I
•
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I
released.
I
2
C bus
2
2
C bus configuration
2
C interfaces are identical except for the pin I/O characteristics. I
2
C specification, supporting the ability to turn power off to the LPC2400
C bus functioning between other devices. This difference should be
SDA
LPC2400
2
C interfaces on the LPC2400 is byte oriented, and has four operating
Rev. 04 — 26 August 2009
SCL
pull-up
resistor
OTHER DEVICE WITH
I
2
C INTERFACE
Chapter 22: LPC24XX I
2
C1 and I
pull-up
resistor
2
C2 are implemented using
OTHER DEVICE WITH
2
C bus (see "The I
I
2
C INTERFACE
2
2
C-bus devices"). This is
C interfaces.
2
C bus will not be
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
2
C0 complies
SDA
SCL
2
C-bus
573 of 792
2
C0/1/2