LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 702
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
92
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.3 Echo <setting>
6.4 Write to RAM <start address> <number of bytes>
Table 632. ISP Set Baud Rate command
Table 633. Correlation between possible ISP baudrates and CCLK frequency (in MHz)
[1]
Table 634. ISP Echo command
The host should send the data only after receiving the CMD_SUCCESS return code. The
host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is
generated by adding raw data (before UU-encoding) bytes and is reset after transmitting
20 UU-encoded lines. The length of any UU-encoded line should not exceed
61 characters(bytes) i.e. it can hold 45 data bytes. When the data fits in less then
20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.
The ISP command handler compares it with the check-sum of the received bytes. If the
check-sum matches, the ISP command handler responds with "OK<CR><LF>" to
Command
Return Code
Description
Example
ISP Baudrate .vs.
CCLK Frequency
10.0000
11.0592
12.2880
14.7456
15.3600
18.4320
19.6608
24.5760
25.0000
Command
Input
Return Code
Description
Example
ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz
[1]
B
CMD_SUCCESS |
INVALID_BAUD_RATE |
INVALID_STOP_BIT |
PARAM_ERROR
This command is used to change the baud rate. The new baud rate is effective
after the command handler sends the CMD_SUCCESS return code.
"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.
A
Setting: ON = 1 | OFF = 0
CMD_SUCCESS |
PARAM_ERROR
The default setting for echo command is ON. When ON the ISP command handler
sends the received serial data back to the host.
"A 0<CR><LF>" turns echo off.
Rev. 04 — 26 August 2009
Chapter 31: LPC24XX On-chip bootloader for flashless parts
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UM10237
© NXP B.V. 2009. All rights reserved.
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