LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 734

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
Fig 146. LLI example
8.2 Programming the GPDMA for scatter/gather DMA
8.3 Example of scatter/gather DMA
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0x0F---
0x10---
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To program the GPDMA for scatter/gather DMA:
See
to a peripheral. The addresses of each line of data are given, in hexadecimal, at the
left-hand side of the figure. The LLIs describing the transfer are to be stored contiguously
from address 0x20000.
The first LLI, stored at 0x20000, defines the first block of data to be transferred, which is
the data stored between addresses 0x0A200 and 0x0AE00:
1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains
2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
3. Write the first linked list item, previously written to memory, to the relevant channel in
4. Write the channel configuration information to the channel Configuration Register and
5. An interrupt can be generated at the end of each LLI depending on the Terminal
four words:
– Source address.
– Destination address.
– Pointer to next LLI.
– Control word.
The last LLI has its linked list word pointer set to 0. The LLIs must be stored in the
memory where the GPDMA has access to (i.e. AHB1 SRAM and external memory).
priority and DMA channel 1 the lowest priority.
the GPDMA.
set the Channel Enable bit. The GPDMA then transfers the first and then subsequent
packets of data as each linked list item is loaded.
Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at
the end of the relevant LLI. The interrupt request must then be serviced and the
relevant bit in the DMACIntTCClear Register must be set to clear the interrupt.
Figure 32–146
0x--200
for an example of an LLI. A rectangle of memory has to be transferred
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
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UM10237
© NXP B.V. 2009. All rights reserved.
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