LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 601

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
9.10 I
9.11 Bus error
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
obtained within a reasonable amount of time, then a forced access to the I
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
and is able to transmit a START condition. The STO flag is cleared by hardware (see
Figure
An I
SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is
possible, and the I
problem must be resolved by the device that is pulling the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit
synchronization), the problem can be solved by transmitting additional clock pulses on the
SCL line (see
the STA flag is set, but no START condition can be generated because the SDA line is
pulled LOW while the I
START condition after every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted, state 0x08 is
entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is transmitted while SDA is
obstructed (pulled LOW), the I
In each case, state 0x08 is entered after a successful START condition is transmitted and
normal serial transfer continues. Note that the CPU is not involved in solving these bus
hang-up problems.
A bus error occurs when a START or STOP condition is present at an illegal position in the
format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
The I
a master or an addressed slave. When a bus error is detected, the I
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in
2
08H
Fig 124. Simultaneous repeated START conditions from 2 masters
C Bus obstructed by a Low level on SCL or SDA
S
2
C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the
2
C hardware only reacts to a bus error when it is involved in a serial transfer either as
22–125).
SLA
2
C bus stays busy indefinitely. If the STA flag is set and bus access is not
Figure
W
18H
2
A
C hardware cannot resolve this type of problem. When this occurs, the
22–126). The I
Rev. 04 — 26 August 2009
2
C bus is considered free. The I
DATA
2
2
C hardware behaves as if a STOP condition was received
C hardware performs the same action as described above.
repeated START earlier
other Master sends
28H
A
2
C hardware transmits additional clock pulses when
S
Chapter 22: LPC24XX I
OTHER MASTER
CONTINUES
Table
2
C hardware attempts to generate a
22–529.
2
retry
08H
P
C interfaces I
2
C block immediately
UM10237
© NXP B.V. 2009. All rights reserved.
S
2
C bus is
SLA
601 of 792
2
C0/1/2