LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 579
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
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LPC2470FET208,551
Manufacturer:
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UM10237_4
User manual
7.2 Address Register I2ADDR
7.3 Comparator
7.4 Shift register I2DAT
7.5 Arbitration and synchronization logic
This register may be loaded with the 7 bit slave address (7 most significant bits) to which
the I
(GC) is used to enable general call address (0x00) recognition.
The comparator compares the received 7 bit slave address with its own slave address (7
most significant bits in I2ADR). It also compares the first received 8 bit byte with the
general call address (0x00). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
This 8 bit register contains a byte of serial data to be transmitted or a byte which has just
been received. Data in I2DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received
data is located at the MSB of I2DAT. While data is being shifted out, data on the bus is
simultaneously being shifted in; I2DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in I2DAT.
In the master transmitter mode, the arbitration logic checks that every transmitted logic 1
actually appears as a logic 1 on the I
1 and pulls the SDA line low, arbitration is lost, and the I
from master transmitter to slave receiver. The I
pulses (on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode
can only occur while the I
Arbitration is lost when another device on the bus pulls this signal LOW. Since this can
occur only at the end of a serial byte, the I
Figure 22–118
Fig 118. Arbitration procedure
2
C block will respond when programmed as a slave transmitter or receiver. The LSB
(1) A device transmits serial data.
(2) Another device overrules a logic 1 (dotted line), transmitted by this I
(3) This I
line low. Arbitration is lost, and this I
transmitted. This I
the new master once it has won arbitration.
SDA line
SCL line
2
C is in Slave Receiver mode but still generates clock pulses until the current byte has been
shows the arbitration procedure.
Rev. 04 — 26 August 2009
2
C will not generate clock pulses for the next byte. Data on SDA originates from
2
C block is returning a “not acknowledge: (logic 1) to the bus.
(1)
1
(1)
2
2
C bus. If another device on the bus overrules a logic
2
C enters Slave Receiver mode.
(2)
3
2
Chapter 22: LPC24XX I
C block generates no further clock pulses.
2
C block will continue to output clock
4
2
C block immediately changes
(3)
2
C master, by pulling the SDA
8
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
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