LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 557
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
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LPC2470FET208,551
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UM10237_4
User manual
5.3.6 Data path
5.3.7 Data path state machine
Table 485. Command path status flags
The CRC generator calculates the CRC checksum for all bits before the CRC code. This
includes the start bit, transmitter bit, command index, and command argument (or card
status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long
response format. Note that the start bit, transmitter bit and the six reserved bits are not
used in the CRC calculation.
The CRC checksum is a 7 bit value:
The card data bus width can be programmed using the clock control register. If the wide
bus mode is enabled, data is transferred at four bits per clock cycle over all four data
signals (MCIDAT[3:0]). If the wide bus mode is not enabled, only one bit per clock cycle is
transferred over MCIDAT0.
Depending on the transfer direction (send or receive), the Data Path State Machine
(DPSM) moves to the WAIT_S or WAIT_R state when it is enabled:
The DPSM operates at MCICLK frequency. Data on the card bus signals is synchronous
to the rising edge of MCICLK. The DPSM has six states, as shown in
Flag
CmdRespEnd
CmdCrcFail
CmdSent
CmdTimeOut
CmdActive
•
•
CRC[6:0] = Remainder [(M(x) × x
G(x) = x
M(x) = (start bit) × x
M(x) = (start bit) × x
Send: The DPSM moves to the WAIT_S state. If there is data in the send FIFO, the
DPSM moves to the SEND state, and the data path subunit starts sending data to a
card.
Receive: The DPSM moves to the WAIT_R state and waits for a start bit. When it
receives a start bit, the DPSM moves to the RECEIVE state, and the data path subunit
starts receiving data from a card.
7
+ x
3
+ 1
39
119
Rev. 04 — 26 August 2009
Description
Set if response CRC is OK.
Set if response CRC fails.
Set when command (that does not require response) is sent.
Response timeout.
Command transfer in progress.
+ ... + (last bit before CRC) × x
+ ... + (last bit before CRC) × x
7
) / G(x)]
Chapter 21: LPC24XX SD/MMC card interface
0
0
, or
Figure
UM10237
© NXP B.V. 2009. All rights reserved.
21–109.
557 of 792
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