LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 358

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
UM10237_4
User manual
9.8.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0xFFE0 C2A8)
9.8.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0xFFE0
9.8.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0xFFE0 C2A4)
Table 338. USB End of Transfer Interrupt Status register (USBEoTIntSt - address
Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt
register. Writing zero has no effect. USBEoTIntClr is a write only register.
Table 339. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address
Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register.
Writing zero has no effect. USBEoTIntSet is a write only register.
Table 340. USB End of Transfer Interrupt Set register (USBEoTIntSet - address
A bit in this register is set when a transfer is requested from the USB device and no valid
DD is detected for the corresponding endpoint. USBNDDRIntSt is a read only register.
Table 341. USB New DD Request Interrupt Status register (USBNDDRIntSt - address
Bit
31:0
Bit
31:0 EPxx
Bit
31:0
Bit
31:0
C2AC)
Symbol
Symbol Value
Symbol
Symbol
EPxx
EPxx
EPxx
0xFFE0 C2A0s) bit description
0xFFE0 C2A4) bit description
0xFFE0 C2A8) bit description
0xFFE0 C2AC) bit description
Value Description
0
1
0
1
Value
0
1
Value
0
1
Rev. 04 — 26 August 2009
Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
No effect.
Clear the EPxx End of Transfer Interrupt request in the
USBEoTIntSt register.
Description
No effect.
Set the EPxx End of Transfer Interrupt request in the
USBEoTIntSt register.
Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
Description
Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.
There is no new DD interrupt request for endpoint xx.
There is a new DD interrupt request for endpoint xx.
Description
Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.
There is no End of Transfer interrupt request for endpoint xx.
There is an End of Transfer Interrupt request for endpoint xx.
Chapter 13: LPC24XX USB device controller
UM10237
© NXP B.V. 2009. All rights reserved.
Reset value
0
358 of 792
Reset
value
0
Reset
value
Reset
value