LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 569
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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Price
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Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
92
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Part Number:
LPC2470FET208,551
Manufacturer:
NXP Semiconductors
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NXP Semiconductors
UM10237_4
User manual
6.11 Status Register (MCIStatus - 0xE008 C034)
Table 503: Data Counter register (MCIDataCnt - address 0xE008 C030) bit description
Note: This register should be read only when the data transfer is complete.
The MCIStatus register is a read-only register. It contains two types of flag:
Table 21–504
Table 504: Status register (MCIStatus - address 0xE008 C034) bit description
Bit
15:0
31:16
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
•
•
Static [10:0]: These remain asserted until they are cleared by writing to the Clear
register (see
Dynamic [21:11]: These change state depending on the state of the underlying logic
(for example, FIFO full and empty flags are asserted and deasserted as data while
written to the FIFO).
Symbol
DataCount Remaining data
-
Symbol
CmdCrcFail
DataCrcFail
CmdTimeOut
DataTimeOut
TxUnderrun
RxOverrun
CmdRespEnd
CmdSent
DataEnd
StartBitErr
DataBlockEnd
CmdActive
TxActive
RxActive
TxFifoHalfEmpty Transmit FIFO half empty.
RxFifoHalfFull
TxFifoFull
RxFifoFull
TxFifoEmpty
RxFifoEmpty
shows the bit assignment of the MCIStatus register.
Section 21–6.12 “Clear Register (MCIClear - 0xE008
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Description
Command response received (CRC check failed).
Data block sent/received (CRC check failed).
Command response timeout.
Data timeout.
Transmit FIFO underrun error.
Receive FIFO overrun error.
Command response received (CRC check passed).
Command sent (no response required).
Data end (data counter is zero).
Start bit not detected on all data signals in wide bus mode. 0
Data block sent/received (CRC check passed).
Command transfer in progress.
Data transmit in progress.
Data receive in progress.
Receive FIFO half full.
Transmit FIFO full.
Receive FIFO full.
Transmit FIFO empty.
Receive FIFO empty.
Chapter 21: LPC24XX SD/MMC card interface
UM10237
C038)”).
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Value
0x0000
NA
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