MC9S08GT32CFDE Freescale Semiconductor, MC9S08GT32CFDE Datasheet - Page 117

• Manufacturer Part Number: MC9S08GT32CFDE
• Description: IC MCU 32K FLASH 20MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT32CFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. Once the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
7.5
Refer to the direct-page register summary in the
assignments for all ICG registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Freescale Semiconductor
Initial conditions:
1) Clock supplied from ATE has 500 µs duty period
2) ICG configured for internal reference with 4 MHz bus
ICG Registers and Control Bits
INCREASES THE FREQUENCY)
(DECREASING ICGTRM
ICGTRM - 128 / (2**n)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
ICGTRM =
n = n + 1
IS n > 8?
(COUNT = # OF BUS CLOCKS / 4)
DECREASES THE FREQUENCY)
MC9S08GB/GT Data Sheet, Rev. 2.3
NO
START TRIM PROCEDURE
INCOMING CLOCK WIDTH
Figure 7-11. Trim Procedure
(INCREASING ICGTRM
ICGTRM = $80, n = 1
ICGTRM + 128 / (2**n)
CASE STATEMENT
ICGTRM =
MEASURE
YES
.
Memory
COUNT > EXPECTED = 500
(RUNNING TOO FAST)
chapter of this data sheet for the absolute address
COUNT = EXPECTED = 500
ICG Registers and Control Bits
Figure 7-11
STORE ICGTRM VALUE
IN NON-VOLATILE
CONTINUE
MEMORY
while the
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