MC9S08GT32CFDE Freescale Semiconductor, MC9S08GT32CFDE Datasheet - Page 138

• Manufacturer Part Number: MC9S08GT32CFDE
• Description: IC MCU 32K FLASH 20MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT32CFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Central Processor Unit (CPU)
138
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
BRCLR n,opr8a,rel
BRN rel
BRSET n,opr8a,rel
BSET n,opr8a
BSR rel
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
CLC
CLI
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Source
Form
Branch if Minus
Branch if Interrupt Mask
Set
Branch if Not Equal
Branch if Plus
Branch Always
Branch if Bit n in Memory
Clear
Branch Never
Branch if Bit n in Memory
Set
Set Bit n in Memory
Branch to Subroutine
Compare and Branch if
Equal
Clear Carry Bit
Clear Interrupt Mask Bit
Clear
Compare Accumulator
with Memory
Operation
Table 8-1. HCS08 Instruction Set Summary (Sheet 3 of 7)
MC9S08GB/GT Data Sheet, Rev. 2.3
(CCR Updated But Operands Not
push (PCH); SP ← (SP) – $0001
push (PCL); SP ← (SP) – $0001
PC ← (PC) + $0002
Uses 3 Bus Cycles
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (Mn) = 0
Branch if (Mn) = 1
Branch if (N) = 1
Branch if (Z) = 0
Branch if (N) = 0
PC ← (PC) + rel
Branch if (I) = 1
Description
Changed)
M ← $00
H ← $00
M ← $00
M ← $00
M ← $00
(A) – (M)
A ← $00
X ← $00
No Test
Mn ← 1
C ← 0
I ← 0
V H I N Z C
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – –
– – – – – – REL
– – – – –
– – – – – –
– – – – – – REL
– – – – – –
– – – – – 0 INH
– – 0 – – – INH
0 – – 0 1 –
– –
on CCR
Effect
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
Freescale Semiconductor
9ED1
9EE1
9E6F
9E61
AD rr
2D rr
0D
0C
1C
8C
C1
D1
2B rr
2A rr
0B
0A
0E
1A
1E
9A
A1
B1
E1
26 rr
20 rr
01
03
05
07
09
0F
21 rr
00
02
04
06
08
10
12
14
16
18
31
41
51
61
71
98
3F
4F
5F
6F
7F
F1
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii
ii
ff
rr
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
rr
rr
rr
rr
3
3
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
5
5
6
1
1
5
1
1
1
5
4
6
2
3
4
4
3
3
5
4